In a PLC system, information is conveyed over conventional, power line media on PLC data signals. The PLC system includes PLC transceivers that operate in accordance with predetermined PLC protocols and standards. The protocols and standards are formulated in view of the processing capabilities of the PLC transceiver equipment and the expected PLC signal transmission characteristics of the PLC system. The protocols and standards, for example, define the spectrum of frequencies used for PLC signal transmissions and how information content and associated overhead (control) data are carried on PLC signals. The arrangement of information content and overhead data within a PLC signal is typically referred to as a frame structure. The frame structure establishes the sequence in which PLC signals containing overhead and information content data are generated for transmission over the PLC system.
When many of the prior art PLC systems, such as orthogonal frequency division multiplexing (“OFDM”) PLC systems, were designed, the lack or limited availability of high speed processing technology dictated the format of PLC signals and, thus, the PLC signal processing operations performed at the prior art PLC transceivers. In addition, prior art PLC system design focused on robustness, or ensuring that a destination PLC transceiver accurately and completely reproduces information content that a source PLC transceiver transmits on a PLC signal over a PLC system. Thus, the desire for robustness, the available processing technology and also expected PLC signal transmission characteristics of the PLC system determined the design parameters of the prior art PLC signal frame structure.
The currently and widely used PLC signal frame structure, which is substantially the same as the frame structure adopted in early prior art PLC systems, includes a payload portion interposed between start and end delimiters. See Gardner, S. et al., “HomePlug Standard Bring Networking to the Home”, http://www.commsdesign.com/main/2001/12/0012feat5.htm, Dec. 12, 2000, incorporated by reference herein. The start and end delimiters include communications overhead data, such as a preamble, destination address, source address, network protocol type and frame check (error correction), which a destination PLC transceiver requires for extracting information content and other processing control data from the PLC signals transmitted by a source PLC transceiver. The payload portion contains a plurality of payload symbols. Each of the payload symbols corresponds to one or more distinct information content data modulated PLC carriers that are to be generated at and transmitted from the PLC transceiver. The PLC carriers that can be modulated with information content are at frequencies distributed across a predetermined PLC frequency spectrum.
The prior art PLC system design also provided that very few modulation methods can be used to modulate a PLC carrier and that all of the PLC carriers that can be generated for a payload symbol are modulated using the same predetermined modulation method (“order of modulation”). The prior art PLC system design preferred the use of a single order of modulation for all PLC carriers because this simplified the overall system design, especially concerning design of the modulator, demodulator, interleaver, deinterleaver, error correction algorithms, etc. This design approach permitted the complexity level of the system to be commensurate with the capabilities of the then existing design techniques, silicon geometries and design densities. In operation, the prior art PLC transceiver attempts to select the highest order of modulation for the PLC carriers, in view of channel quality data indicating expected PLC signal transmission performance, to obtain the most data bits per available PLC carrier within a predetermined PLC frequency spectrum, thereby maximizing data throughput rate.
Although the prior art PLC system design does not provide that the order of modulation of an individual PLC carrier can be dynamically changed in view of channel quality data particular to an individual PLC carrier, this result was tolerated or required in view of the processing speed limitations of technologies available in the prior art and to ensure reliable and accurate transfer of information content using PLC signals.
Since the development of the prior art PLC frame structure design, which continues to be used in a vast majority of current PLC systems, advanced, higher speed silicon implementations have become available and cost effective for use in a PLC transceiver. PLC systems and PLC transceivers, however, continue to utilize the prior art PLC system frame structure design. In many circumstances, this continued prior art requirement that all PLC carriers that can be generated for a payload symbol are modulated at a single order of modulation unnecessarily limits the maximum available data throughput rate for the PLC system.
Therefore, a need exists for a system and method for maximizing data throughput rate in a PLC system in view of available higher speed data processing technologies and while also permitting that existing PLC transceivers can continue to be used without difficult or costly modifications.